The PIC16F887 microcontroller has several independent serial communication modules and each of them can be configured to operate in several different modes, which make them irreplaceable in many situations. Remember what we advised you about the CCP modules as the same applies here. Don’t burden yourself with details on the operation of all of them, just select one and learn only what you really need.The USART is one of the oldest serial communication systems. The modern versions of this system are upgraded and called somewhat differently - EUSART.EUSART. The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communication peripheral unit.

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It is also known as Serial Communications Interface (SCI). It contains all clock generators, shift registers and data buffers necessary to perform a serial data transfer independently of the main program execution. As its name states, apart from using the clock for synchronization, this module can also establish asynchronous connection, which makes it unique for some of the applications. For example, in case it is difficult or impossible to provide special channels for clock and data transfer (for example, radio or infrared remote control), the EUSART module is definitely the best possible solution. The EUSART system integrated into the PIC16F887 microcontroller has the following features:. Full-duplex asynchronous transmit and receive;.

Programmable 8- or 9-bit wide characters;. Address detection in 9-bit mode;. Input buffer overrun error detection; and. Half-duplex communication in synchronous mode.EUSART IN ASYNCHRONOUS MODEThe EUSART transmits and receives data using a standard non-return-to-zero (NRZ) format.

As can be seen in figure below, this mode doesn’t use clock signal, while the format of data being transferred is very simple. In order to enable data transmission via the EUSART module, it is necessary to configure this module to operate as a transmitter. In other words, it is necessary to define the state of the following bits:. TXEN = 1 - EUSART transmitter is enabled by setting the TXEN bit of the TXSTA register. SYNC = 0 - EUSART is configured to operate in asynchronous mode by clearing the SYNC bit of the TXSTA register. SPEN = 1 - By setting the SPEN bit of the RCSTA register, EUSART is enabled and the TX/CK pin is automatically configured as an output. If this bit is simultaneously used for some analogue function, it must be disabled by clearing the corresponding bit of the ANSEL register.The central part of the EUSART transmitter is the shift register TSR which is not directly accessible by the user.

In order to start data transfer, the EUSART transmitter must be enabled by setting the TXEN bit of the TXSTA register. Data to be sent should be written to the TXREG register, thus causing the following sequence of events to occur:. Byte will be immediately transferred to the shift register TSR;. The TXREG register remains empty, which is indicated by setting the flag bit TXIF of the PIR1 register. If the TXIE bit of the PIE1 register is set, an inter rupt will be generated. However, the flag is set regardless of whether an inter rupt is enabled or not and it cannot be cleared by software, but by writing new data to the TXREG register.

Control electronics ‘pushes’ data toward the TX pin in synchronization with internal clock: START bit (0). STOP bit (1). When the last bit leaves the TSR register, the TRMT bit of the TXSTA register is automatically set. If the TXREG register has received a new character data in the meantime, the whole procedure will be immediately repeated after the STOP bit of the previous character has been transmitted.The 9-bit data transfer is enabled by setting the TX9 bit of the TXSTA register. The TX9D bit of the TXSTA register is the ninth and most significant data bit.

When transferring 9- bit data, the TX9D data bit must be written prior to writing the 8 least significant bits into the TXREG register. All nine bits of data will be transferred to the TSR shift register immediately after the TXREG write is complete.EUSART ASYNCHRONOUS RECEIVER.

Similar to the activation of EUSART transmitter, in order to enable the receiver it is necessary to configure the following bits:. CREN = 1 - EUSART receiver is enabled by setting the CREN bit of the RCSTA register;. SYNC = 0 - EUSART is configured to operate in asynchronous mode by clearing the SYNC bit stored in the TXSTA register; and. SPEN = 1 - By setting the SPEN bit of the RCSTA register, EUSART is enabled and the RX/DT pin is automatically configured as an input. If this bit is simultaneously used for some analogue function, it must be disabled by clearing the corresponding bit of the ANSEL register.When this first and necessary step is accomplished and the START bit is detected, data is transferred to the shift register RSR through the RX pin. When the STOP bit has been received, the following occurs:.

Data is automatically sent to the RCREG register (if empty);. The flag bit RCIF is set and an interrupt, if enabled by the RCIE bit of the PIE1 register, occurs.

Similarly to the transmitter, the flag bit is automatically cleared by reading the RCREG register. Bear in mind that this is a two character FIFO register (first-in, first-out) which allows a simultaneous reception of two data bytes;. IIf the RCREG register is occupied (contains two bytes) and the shift register detects new STOP bit, the overflow bit OERR will be set. In this case, a new coming data is lost, and the OEER bit must be cleared by software. It is done by clearing and resetting the CREN bit;Note: it is not possible to receive new data as far as the OERR bit is set. If the STOP bit is driven low (0), the FERR bit of the RCSTA register detecting receive error will be set; and.

To enable 9-bit data reception, it is necessary to set the RX9 bit of the RCSTA register.RECEIVE ERROR DETECTIONThere are two types of errors which the microcontroller can automatically detect. The first one is called Framing error and occurs when the receiver does not detect the STOP bit at the expected time. Such an error is indicated by the FERR bit of the RCSTA register. If this bit is set, the last received data may be incorrect. Here are several things important to know:. A Framing error does not generate an interrupt by itself;. If this bit is set, the last received data has an error;.

A framing error (bit set) does not prevent reception of new data;. The FERR bit is cleared by reading received data, which means that check must be done prior to reading data; and. The FERR bit cannot be cleared by software.

If needed, it can be cleared by clearing the SPEN bit of the RCSTA register. It will simultaneously cause the whole EUSART system to be reset.There are two types of errors which the microcontroller can automatically detect. The first one is called Framing error and occurs when the receiver does not detect the STOP bit at the expected time. Such an error is indicated by the FERR bit of the RCSTA register. If this bit is set, the last received data may be incorrect. Here are several things important to know:. A Framing error does not generate an interrupt by itself;.

If the FERR bit is set, the last received data has an error;. A framing error (bit set) does not prevent new data from being received;. The FERR bit is cleared by reading received data, which means that check must be done prior to reading data; and. Indian driving licence check online. The FERR bit cannot be cleared by software.

If needed, it can be cleared by clearing the SPEN bit of the RCSTA register. It will simultaneously cause the whole EUSART system to be reset.Another type of error is called Overrun Error.

As previously mentioned, the FIFO memory can receive two bytes. An overrun error will be generated on attempt to receive the third character.

Simply put, there is no space for another one byte and an error is unavoidable. When this happens the OERR bit of the RCSTA register is set. The consequences are the following:. Data already stored in the FIFO registers (two bytes) can be normally read;. No additional data will be received until the OERR bit is cleared; and. This bit is not directly accessed.

To clear it, it is necessary to clear the CREN bit of the RCSTA register or reset the whole EUSART system by clearing the SPEN bit of the RCSTA register.9-BIT DATA RECEIVEApart from receiving standard 8-bit data, the EUSART system supports 9-bit data reception. On the transmit side, the ninth bit is ‘attached’ to the original byte directly before the STOP bit.

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On the receive side, when the RX9 bit of the RCSTA register is set, the ninth data bit will be automatically written to the RX9D bit of the same register. After receiving this byte, it is necessary to take care of how to read its bits- the RX9D data bit must be read prior to reading 8 least significant bits of the RCREG register. Otherwise, the ninth data bit will be cleared. ADDRESS DETECTIONWhen the ADDEN bit of the RCSTA register is set, the EUSART module is able to receive only 9-bit data, whereas all 8-bit data will be ignored. Although it seems like a restriction, such modes enable serial communication between several microcontrollers.

The principle of operation is simple. Master device sends a 9-bit data representing the address of one slave microcontroller. However, all of them must have the ADDEN bit set because it enables address detection. All slave microcontrollers, sharing the same transmission line, receive this data (address) and automatically check whether it matches their own address. The slave device in which the address match occurs, must disable address detection by clearing its ADDEN bit.

CSRC - Clock Source Select bit - is used to for the clock source selection. It is used only in synchronous mode.

1 - Master mode. Clock is generated internally from Baud Rate Generator. 0 - Slave mode. SPEN - Serial Port Enable bit.

1 - Serial port enabled. ABDOVF - Auto-Baud Detect Overflow bit is only used in asynchronous mode during baud rate detection. 1 - Auto-baud timer has overflowed. 0 - Auto-baud timer has not overflowed.RCIDL - Receive Idle Flag bit is only used in asynchronous mode. 1 - Receiver is idle. 0 - START bit has been received and data receive is in progress.SCKP - Synchronous Clock Polarity Select bit.

The logic state of this bit varies depending on which EUSART mode is active.Asynchronous mode:. 1 - Transmit inverted data to the RC6/TX/CK pin.

0 - Transmit non-inverted data to the RC6/TX/CK pin.Synchronous mode:. 1 - Synchronization on the clock rising edge.

0 - Synchronization on the clock falling edge.BRG16 16-bit Baud Rate Generator bit - determines whether the SPBRGH register will be used, i.e. Whether the BRG timer will have 8 or 16 bits. 1 - 16-bit baud rate generator is used.

0 - 8-bit baud rate generator is used.WUE Wake-up Enable bit. 1 - Receiver waits for a falling edge on the RC7/RX/DT pin to wake up the microcontroller from sleep mode.

0 - Receiver operates normally.ABDEN - Auto-Baud Detect Enable bit is used in asynchronous mode only. 1 - Auto-baud detect mode is enabled. Bit is automatically cleared on baud rate detection. 0 - Auto-baud detect mode is disabled.Let's do it in mikroBasic. ' In this example, internal EUSART module is initialized and set to send back the' message immediately after receiving it. Baud rate is set to 9600 bps. The pro'gram uses UART library routines UART1init, UART1WriteText, UART1DataReady,'UART1Write and UART1Read.dim uartrd as bytemain:ANSEL,ANSELH = 0 ' Configure AN pins as digitalCM1CON0.C1ON = 0 ' Disable comparatorsCM2CON0.C2ON = 0UART1Init(9600) ' Initialize UART module at 9600 bpsDelayms(100) ' Wait for UART module to become stableUART1WriteText('Start')while 1 ' Endless loopif (UART1DataReady ' If data is received,uartrd = UART1Read ' read it,end ifUART1Write(uartrd) ' and send it back via UARTwend.

In Short Data transmission via asynchronous EUSART communication:. The desired baud rate should be set by using bits BRGH (TXSTA register) and BRG16 (BAUDCTL register) and registers SPBRGH and SPBRG.

The SYNC bit (TXSTA register) should be cleared and the SPEN bit should be set (RCSTA register) in order to enable serial port. The TX9 bit of the TXSTA register should be set on 9-bit data transmission. Data transmission is enabled by setting the TXEN bit of the TXSTA register. Otherwise, if the microcontroller to be programmed is a peripheral of some more complex device (for example, a PC) then it should operate as a slave. As such, it always has to wait for data transmission request to be sent by the master device.SPI MODEThe SPI mode allows 8 bits of data to be transmitted and received simultaneously using 3 input/output lines:. SDO - Serial Data Out - transmit line;.

SDI - Serial Data In - receive line; and. SCK - Serial Clock - synchronization line.Apart from these three lines, there is the forth line (SS) as well which may be used if the microcontroller exchanges data with several peripheral devices. Refer to figure below.SS - Slave Select - is an additional line used for specific device selection. It is active only when the microcontroller is in slave mode, i.e. When the external - master device requires data exchange.The MSSP module uses in total of 4 register when set to SPI mode:. SSPSTAT - status register. SSPCON - control register.

SSPBUF - buffer register. SSPSR - shift register (not directly available)The first three registers are writable/readable and can be changed at any moment, while the forth register, since not available, is used for converting data into ‘serial’ format. The Shift register (SSPRS) is directly connected to the microcontroller pins and used for serial data transmission. The SSPRS register has its input and output so as the data can be shifted in and out. In other words, each bit appearing on the input (receive line) simultaneously shifts another bit toward the output (transmit line).The SSPBUF register (Buffer) is part of memory used to temporarily hold the data prior to being sent or immediately after being received.

After all 8 bits of data have been received, the byte is moved from the SSPRS to the SSPBUF register. Such operation allows the next byte to be received before reading the data that has just been received. Any write to the SSPBUF register during data transmission/reception will be ignored. From the programmers’ point of view, this register is considered the most important as being most frequently accessed.Namely, if we disregard mode settings for a moment, data transfer via SPI actually comes to data write and read to and from this register, while another ‘acrobatics’ such as moving registers are automatically performed by hardware.Let's do it in mikroBasic.

' In this example, PIC microcontroller (master) sends data byte to peripheral chip' (slave) via SPI. Step 4.The SSPSR register is full once 8 bits of data have been received. It is indicated by setting the BF bit of the SSPSTAT register and the SSPIF bit of the PIR1 register. The received data (one byte) is automatically moved from the SSPSR register to the SSPBUF register. Since serial data transmission is performed automatically, the rest of the program is normally executed while the data transmission is in progress. In this case, the function of the SSPIF bit is to generate an interrupt when one byte transmission is completed. Step 5.Finally, the data stored in the SSPBUF register is ready to use and should be moved to a desired register.

I 2C MODEI 2C mode ( Inter IC Bus) The I2C mode (Inter IC Bus) is especially suitable when the microcontroller and an integrated circuit, which the microcontroller should exchange data with, are within the same device. It is usually another microcontroller or a specialized, cheap integrated circuit belonging to the new generation of the so called ‘smart peripheral components’ (memory modules, temperature sensors, real-time clocks etc.)Similar to serial communication in SPI mode, data transfer in I2C mode is synchronous and bidirectional. This time only two pins are used for data transmission. These are the SDA (Serial Data) and SCL (Serial Clock) pins. The user must configure these pins as inputs or outputs by means of the TRISC bits.By observing particular rules (protocols), this mode enables up to 122 different components to be simultaneously connected in a simple way by using only two valuable I/O pins. Let’s take a look at how it works:Clock, necessary to synchronize the operation of both devices, is always generated by the master device (a microcontroller) and its frequency directly affects the baud rate. Even though there is a protocol allowing maximum 3,4 MHz clock frequency (so called highspeed I2C bus), this book covers only the most frequently used protocol the clock frequency of which is limited to 100 KHz.

There is no limitations for minimum frequency.When master and slave components are synchronized by the clock, every data exchange is always initiated by the master. Once the MSSP module has been enabled, it waits for a Start condition to occur. The master device first sends the START bit (a logic zero) through the SDA pin, then a 7-bit address of the selected slave device, and finally, the bit which requires data write (0) or read (1) to the device. In other words, eight bits are shifted to the SSPSR register following the start condition.

All slave devices sharing the same transmission line will simultaneously receive the first byte, but only one of them has the address to match and receives the whole data. WCOL Write Collision Detect bit. 1 - Collision detected. Write to the SSPBUF register was attempted while the I2C conditions were not valid for transmission to start. 0 - No collision.SSPOV Receive Overflow Indicator bit. 1 - A new byte is received before reading the previously received data. Since there is no space for new data receive, one of these two bytes must be cleared.

GCEN - General Call Enable bitIn I²C slave mode only. 1 - Enables interrupt when a general call address (0000h) is received in the SSPSR.

0 - General call address disabled.ACKSTAT - Acknowledge Status bitIn I²C Master Transmit mode only. 1 - Acknowledge was not received from slave. 0 - Acknowledge was received from slave.ACKDT - Acknowledge data bitIn I²C Master Receive mode only. 1 - Not Acknowledge. 0 - Acknowledge.ACKEN - Acknowledge Sequence Enable bitIn I²C Master Receive mode. 1 - Initiate acknowledge condition on the SDA and SCL pins and transmit the ACKDT data bit. It is automatically cleared by hardware.

0 - Acknowledge condition is not initiated.RCEN - Receive Enable bitIn I²C Master mode only. 1 - Enables data receive in I 2C mode. 0 - Receive disabled.PEN - STOP condition Enable bitIn I²C Master mode only. 1 - Initiates STOP condition on the SDA and SCL pins.

This bit is automatically cleared by hardware. 0 - STOP condition is not initiated.RSEN - Repeated START Condition Enabled bitIn I²C master mode only. 1 - Repeted START condition initiated on the SDA and SCL pins. This bit is automatically cleared by hardware.

0 - Repeated START condition is not initiated.SEN - START Condition Enabled/Stretch Enabled bitIn I²C Master mode only. 1 - Initiates START condition on the SDA and SCL pins. This bit is automatically cleared by hardware. 0 - START condition is not initiated.I 2C in Master ModeThe most common case is that the microcontroller operates as a master and a peripheral component as a slave.

This is why this book covers just this mode. It is also considered that the address consists of 7 bits and a target device contains only one microcontroller (single-master device).In order to enable MSSP module in this mode, it is necessary to do the following. Set baud rate (SSPADD register), turn off slew rate control (by setting the SMP bit of the SSPSTAT register) and select master mode (SSPCON register). After all these preparations have been finished and the module has been enabled (SSPCON register:SSPEN bit), it is necessary to wait for internal electronics to signal that everything is ready for data transmission, i.e. The SSPIF bit of the PIR1 register is set.This bit should be cleared by software and after that the microcontroller is ready to exchange data with peripherals.DATA TRANSMISSION IN I2C MASTER MODEData transmission on the SDA pin starts with a logic zero (0) which appears upon setting the SEN bit of the SSPCON2 register.

Even enabled, the microcontroller has to wait a certain time before it starts communication. It is the so called ‘Start condition’ during which internal preparations and checks are performed. If all conditions are met, the SSPIF bit of the PIR1 is set and data transmission starts as soon as the SSPBUF register is loaded. When address match occurs, the microcontroller has to wait for the acknowledge data bit.

The slave device acknowledges address match by clearing the ASKSTAT bit of the SSPCON2 register. If the match has properly occurred, all data bytes are transmitted in the same way.Data transmission ends by setting the SEN bit of the SSPCON2 register. The STOP condition occurs, which enables the SDA pin to receive pulses:Start - Address - Acknowledge - Data - Acknowledge.Data - Acknowledge - Stop!Data Reception in I 2C Master ModePreparations for data reception are similar to those for data transmission, with exception that the last bit of the first sent byte (containing address) is set to logic one (1).

It specifies that master expects to receive data from the addressed slave device. Let’s see what happens within the microcontroller:After internal preparations are finished and the START bit is set, the slave device starts sending one byte at a time. These bytes are stored in the serial register SSPSR. Each data is, after receiving the last eighth bit, loaded to the SSPBUF register from where it can be read. Reading this register causes the acknowledge bit to be automatically sent, which means that the master device is ready to receive new data.Likewise, data reception ends by setting the STOP bit.

Start - Address - Acknowledge - Data - Acknowledge. Data - Acknowledge - Stop!In this pulse sequence, the acknowledge bit is sent to the slave device.BAUD RATE GENERATORIn order to synchronize data transmission, all events taking place on the SDA pin must be synchronized with a clock generated in the master device by a simple oscillator the frequency of which depends on the microcontroller’s main oscillator frequency, the value written to the SSPADD register and the current SPI mode as well.The clock frequency of the mode described in this book depends on selected quartz crystal and the SPADD register. Figure below shows the formula used to calculate it.

Let's do it in mikroBasic. ' In this example, PIC MCU is connected to 24C02 EEPROM via SCL and SDA pins. The program' sends one byte of data to the EEPROM address 2.

Then, it reads data via I2C from EEPROM' and sends it to PORTB in order to check if the data has been successfully written.main:ANSEL = ANSELH = PORTB = TRISB = 0 ' All pins are digital.

Salam Kapasitorr!!!Pada postingan kali ini kita akan belajar mengenai komunikasi serial antar 2 mikrokontroller. Sebelum kita lanjut, ada baiknya kita tahu terlebih dahulu arti dari komunikasi serial. Komunikasi serial adalah metode pengiriman data dimana data yang dikirim satu per satu. Jenis komunikasi yang akan kita gunakan adalah USART ( Universal Syncronous Asyncronous Receiver Transmitter). Maksud dari USART tersebut, kita bisa menggunakan 2 mode yaitu mode Syncrounous dan mode Asyncronous. Perbedaannya terletak pada sumber clocknya. Jika pada syncronous, sumber clocknya harus sama jadi diperlukan PIN yang bertindak sebagai Clock.

Pin - pin tersebut adalah RXD, RXD, XCK. Sedangkan pada Asyncronous hanya diperlukan 2 Pin saja yaitu RXD & TXD.Langsung ke bagian setting programnya. Berikut hal - hal yang harus dilakukan untuk mengaktifkan fitur USART.